1. Field of the Invention
The invention relates to a method of forming a gate. More particularly, the invention relates to a method of forming a gate in a recess that includes a lower portion that is substantially wider than an upper portion.
2. Description of the Related Art
As semiconductor devices become highly integrated, active regions of semiconductor devices and various conductive structures formed on the active region(s) are decreasing in size. Accordingly, channel lengths of metal-oxide semiconductor (MOS) transistors may be less than several micrometers.
As a channel length of a MOS transistor becomes shorter, voltages applied to source, drain and/or channel regions of the MOS transistor, have a larger influence on an electric field. This phenomenon is often called “a short channel effect.” As a result of the short channel effect, e.g., a threshold voltage may drop because the channel region may be affected not only by a gate voltage but also by electrons in a depletion region, an electric field and a voltage distribution of the source/drain regions.
Generally, a dynamic random-access memory (DRAM) device may require a high operating speed and a large data storage capacitance. Generally, as many unit cells as possible may be formed on a semiconductor substrate. Thus, a gate size of the DRAM device may have to be reduced in order to form a semiconductor device having a high degree of integration. The reduction of the gate size may result in a decrease of a channel length. A reduction of the channel length may cause, via the short channel effect, an operational defect, e.g., a dynamic refresh defect or a static refresh defect.
Transistors having a recessed channel region have been developed as a result of efforts for reducing and/or suppressing the short channel effect. In such transistors, a gate electrode of the transistor may be formed to fill up a gate recess formed at an upper portion of a semiconductor substrate so that a channel length sufficiently long for the operation of the transistor may be ensured in spite of the reduction of the gate size.
Such a recessed gate may be formed by a technique that includes sufficiently filling the gate recess with a conductive material. However, filling up the gate recess without a void is generally difficult because of a small width of the gate recess. Transistors having a gate recess with a lower portion substantially wider than an upper portion, have also been developed. However, in such transistors with a gate recess having a relatively wider lower portion, an opening of the gate recess may be closed before the wider lower portion of the gate recess is sufficiently filled with a conductive material, and a void may be formed in the gate recess.
When a void formed at a central portion of the gate recess does not directly make contact with a gate insulation layer formed on an inner sidewall of the gate recess, the void may not cause an operational defect of the transistor. However, the void may move in the gate recess and may make contact with the gate insulation layer during subsequent processing, and electrical characteristics of the transistor may be deteriorated.
FIG. 1 illustrates a cross-sectional view of a recessed gate having a void.
Referring to FIG. 1, a void 14 may be formed in a recessed gate 16, which may be formed on a substrate 10 to fill up a recess having a lower portion substantially wider than an upper portion. When the recessed gate 16 is formed using polysilicon, silicon atoms included in the recessed gate 16 may freely move in the recessed gate 16, so that the void(s) 14 may move in the recessed gate 16, and may make contact with a gate oxide layer 12 formed between the recessed gate 16 and the substrate 10. When the void 14 makes contact with the gate oxide layer 12, a leakage current may be generated, and a threshold voltage distribution of the MOS transistor may increase. Thus, electrical characteristics of the MOS transistor may be deteriorated, and a production yield of a semiconductor device may be reduced.